The need to protect integrated circuit input and output ports from damages caused by electrostatic discharge is well known, and various types of structures have been employed for this purpose. One type of structure employs metal-oxide-semiconductor field-effect transistors (MOSFETs) with grounded gates. One or more parasitic bipolar devices associated with the MOSFET act to provide a leakage path at high input voltages to protect subsequent circuitry. See, for example, “Recent Developments in ESD Protection for RF IC's”, by Wang, Design Automation Conference, 2003, Proceedings of the ASP-DAC 2003, page 171 Wang; and “On-Chip ESD Protection for Integrated Circuits,” A. Wang, Kluwer Academic, 2002. However, this type of ESD protection structure may present a large parasitic capacitive load to the protected device, and may thus be unsuitable for high-performance devices operating at high frequencies, such as, for example, 2.4 or 5.2 GHz for wireless local area networks.
Another type of ESD structure employs stacked diodes constructed from, for example, P+ diffusions and n-wells, as shown in FIG. 1. Although FIG. 1 only shows three stages of stacked diodes, a larger number of these diodes could be employed depending on the requirements of the application. As discussed by Voldman in “the State of the Art of Electrostatic Discharge Protection”, IEEE J Solid-State Ckcts 34 #9 September 1999, a parasitic leakage path formed by parasitic bipolar transistors associated with the structure for injected minority carriers through the n-well into the substrate causes some of the ESD current of each diode to be shunted to the substrate, as shown by the equivalent circuit in FIG. 1. As a consequence, a forward voltage between an I/O pad and a power rail or ground for a given input current is greatly reduced, and high trigger voltages are not achievable at small leakage currents.
In “Investigation of ESD Devices in 0.18 micron SiGe BiCMOS Process”, 41st Annual Reliability Physics Symposium, Dallas, Tex., 2003, p. 357, Chen et. al. have proposed the use of a modified structure of stacked-diodes, each having a P+ diffusion and a N+ diffusion separated by a shallow trench isolation (STI) in a P-well, and a buried N+ layer below the P-well, as shown in FIG. 2. The diodes are separated from both shallow and deep trench isolations. The structure illustrated in FIG. 2 avoids the limitations of the conventional stacked-diode structure shown in FIG. 1 by eliminating parasitic currents to the substrate, as shown by the equivalent circuit in FIG. 2. This modified structure causes the base of the parasitic bipolar transistor to move to the N+ buried layer under the P-well, and thus results in a considerable increase in the forward voltage for a fixed leakage current. The forward voltage, however, is still limited by the voltage drop in the shallow P-well region between the buried N+ layer and the shallow-trench isolation between the P+ and N+ diffusion regions. Furthermore, this structure is designed specifically for ESD protection and requires separate processing steps and characterization in addition to those required for fabricating the protected circuit.
Therefore, there is need for an ESD protection scheme for high-performance radio-frequency input ports, which provides high hold-off (or trigger) voltages with low leakage and minimal parasitic capacitance, and which is can be constructed during processing of the protected circuits without the need for additional processing steps.